a. Field of the Invention
The present invention relates to semiconductor devices and, more particularly, to a method and circuit for increased device reliability through protection against the effects of hot carriers.
b. Description of the Background
Advances in the semiconductor industry continue to provide smaller device geometries. As geometries have been reduced, some failure mechanisms have become more pronounced. One of the most significant contributors to device failure in sub-micron range devices is hot carrier injection (HCI), also referred to as hot carrier effect. Hot carrier injection is an effect where high-energy charges are injected into the gate dielectric of a MOSFET device and may become lodged in the dielectric. Trapped charges tend to accumulate over time and affect the turn-on voltage, and drain current of transistors and may eventually lead to the failure of the device. Carrier injection is a function of field strength between the source and drain of a transistor. Field strength is a function of the physical distance and voltage difference between source and drain channels. The reduction in geometries of semiconductor devices has been accompanied by a reduction in the operating voltage of the device. Many logic devices that operated at 5 volts a number of years ago now operate at 3.3 volts or less.
Many devices have input/output buffers that meet TTL specifications. However, many of these devices generate an output voltage level that is close to the positive supply voltage when generating a logic one voltage. When a device having a 5 volt supply is interfaced with a device having a 3.3 volt power, a voltage near 5 volts may be presented to the 3.3 volt device as a logic one level. The input structure of the 3.3 volt device may employ diodes to accommodate the 5 volt level. Output drivers for a 3.3 volt device, and more specifically n-channel devices employed to drive a logic zero value, however, may experience a voltage difference near 5 volts. This higher voltage results in higher field strength for n-channel devices and may result in higher HCI rates and reduced device reliability.
One approach to reducing HCI effects is to employ longer channel transistors. A longer channel device must be wider in order to provide the same current capabilities as a shorter channel device, resulting in greater area being employed for the drive transistors and higher cost for the device. A new method is needed that provides the reduced HCI susceptibility of longer channel devices but without the area and cost penalties of longer devices.
The present invention overcomes the disadvantages and limitations of the prior art by first employing a long channel transistor to discharge a signal node to a voltage level at which shorter channel devices may be enabled. This provides lower field strength across the short channel device, reducing charges deposited in the dielectric layer. The long channel transistor is less susceptible to HCI damage such that the long and short channel transistor combination provides higher device reliability.
The invention therefore may comprise a high reliability output driver comprising: a first transistor having a first gate channel length, the first transistor being operatively connected between an output node and a first voltage terminal, a second transistor having a second gate channel length wherein the second gate channel length is greater than the first gate channel length, the second transistor being operatively connected between the output node and the first voltage terminal, a drive signal line connected to the gate of the first transistor, and a delay element having an input connected to the drive signal line and an output connected to the gate of the second transistor.
The present invention employs a long channel device that is designed to operate across a first voltage range, such as zero volts to 5.25 volts, for example, and employs a short channel transistor that is designed to operate at a second voltage range, such as zero volts to 3.5 volts, for example. The two-transistor architecture of the present invention may be employed to charge or discharge a signal node with lower surge current than may be exhibited by a single transistor. The method of the present invention is applicable to external driver circuitry and to internal circuitry where different voltage levels may be encountered.
The invention may further comprise a method for increased reliability in a semiconductor driver comprising: connecting a first transistor between a voltage terminal and an output node, connecting a second transistor between the voltage terminal and the output node wherein the second transistor has a gate channel length that is less than the gate channel length of the first transistor, applying a first gating signal to the gate of the first transistor, applying the first gating signal to the input of a delay element to generate a delayed output, and applying the delayed output to the gate of the second transistor.
Advantageously, the present invention provides higher reliability and desirable drive characteristics without incurring the space and cost penalties of large long channel devices.